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Guild: wafer.space Community
Channel: 🏗️ - Designing / analog / I need a quick&dirty current reference.
After: 2026-05-31 11:59 p.m.
Before: 2026-07-01 12:00 a.m.
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[2026-06-01 6:25 a.m.] 246tnt
That's what I usually do but I was hoping for something with a bit less Vdd dependence ...
Here say I make by 30 uA at 3.3V nominal. Voltage across nmos will be say ~ 1.5V so I have R = (3.3 - 1.5) / 30u = ~ 60k.  When going to 5V, the 1.5V drop is much less significant so I have 3.5V across resistor and not 1.8V anymore and I go to 58 uA. Simulating it's actually a bit worse than that and then if you had corners, you go even more off.

So I was hoping for something that at least reduces the Vdd dependence somewha.t


[2026-06-01 6:27 a.m.] 246tnt
And AFAICT the widlar source does nothing to help that.


[2026-06-01 9:07 a.m.] 246tnt


{Attachments}
2026-06_media/2026-06-01_562x652_scrot-4CF22.png


[2026-06-01 9:07 a.m.] 246tnt
That's what I think I'll end up with.


[2026-06-01 9:08 a.m.] 246tnt
Bigger that I would have liked, but should be decent enough.


[2026-06-01 9:36 a.m.] 246tnt
or actually might use the same topology but in nmos, makes it a bit smaller.


[2026-06-01 1:56 p.m.] namibj
Stack mos diodes; tap resistor off that intermediate into a current mirror? You have headroom at these Vdd's


[2026-06-01 2:11 p.m.] 246tnt
Problem is solved. The above works.
This is a temp sweep from 15C to 50C (realistic operating range) with VDD from 3 to 5.  Typical corner. And this goes from 31uA to 37uA.
Sweeping across all transitor and resistor corners and vdd and temp, I get from 22uA to 55uA which is good enough for this application.

{Attachments}
2026-06_media/2026-06-01_1718x1418_scrot-EA878.png


[2026-06-01 2:15 p.m.] namibj
Yay


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Exported 9 message(s)
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